The majority of current and foreseeable electronic devices are designed to operate using direct current (DC) power at a voltage which is substantially constant and often, particularly for modern digital circuits which may be formed as integrated circuits of high integration density, must be very closely regulated even when subject to large changes in load current. To provide such regulation, many different voltage converter topologies have been developed. Of these various topologies the so-called buck converter has become very widely used due to its simplicity and the small number of elements required; essentially two switches, an inductor and an output filter capacitor, which lead to the highly desirable characteristics of low cost and high power density.
A buck converter is characterized by having an inductor in series with the load and switches that conduct in a complementary fashion such that when the inductor is connected to the power input, the increasing current in the inductor causes a voltage which is opposite to or “bucks” the input voltage while, when the inductor is disconnected from the input power, decreasing current, referred to as freewheel current, supplied through the other switch causes a voltage which supplies additional current to the load. Of course, such a mode of operation causes a voltage ripple (hereinafter referred to as an inductor ripple) which varies in magnitude with the current drawn by the load and generally must be filtered by a large capacitance. As current is drawn by the load and the capacitor is alternately charged by current from the inductor and discharged to the load, a ripple voltage (referred to hereinafter as capacitor ripple) will appear across the capacitor. The magnitude of the capacitor ripple will be determined by the value of the filter capacitor and the amount of current drawn by the load. The regulated output voltage is determined by the relative duty cycles of the two switches which is usually controlled by a feedback arrangement from the converter output or the point of load (POL).
However, the response to changes in load of a buck converter is less than ideal and load transients have been generally accommodated by the filter capacitor during the short period required to adjust the duty cycle of the switches to provide more current through the inductor. Thus a large value of the filter capacitor has been desirable to limit voltage reduction when load current increases as well as to limit capacitor ripple. Particularly severe load transients are characteristic of digital logic circuits such as processors capable of operating at high clock speeds. More recently, stringent voltage regulation specifications have required provision of filter capacitors at the point of load where the size of the filter capacitor becomes relatively critical and limits the capacitance value that can be provided. Thus, to improve transient response of buck converters such that the filter capacitance may be decreased, a so-called V2 control architecture has been developed and is favored due to its simplicity and ease of implementation as well as its effectiveness in increasing transient response.
The basic concept of V2 control is to sense the current drawn by the load and provide that current information in addition to the output voltage information as feedback to control the duty cycle of the switches so that control can be asserted more rapidly and strongly at the onset of increased load current draw. Such a control architecture has conveniently used the equivalent series resistance (ESR) of the filter capacitor as a current sensor. Since current sensing is difficult, particularly at high current and low voltage, the equivalent series resistance (ESR) of the filter capacitor has been used as a small resistor for sensing inductor current. However, smaller and higher quality (e.g. ceramic) capacitors such as are used at the point of load have a much smaller ESR than large filter capacitors capable of accommodating large load transients as alluded to above. Thus the total ripple waveform appearing at the inductor output and the power converter output and comprising inductor ripple and capacitor ripple components (which differ in waveform and phase) possibly in somewhat different proportions (e.g. if they are obtained at different locations in the circuit having non-ideal conductors even if schematically depicted as the same node) is fed back to control the switches.
However, with capacitors that exhibit a very small ESR, the V2 control architecture suffers from pulse-skipping oscillation instability which, as will be discussed in greater detail below, occurs at large load current when the capacitor ripple becomes dominant in the total ripple waveform, particularly in view of the reduced inductor ripple voltage developed when the ESR of the filter capacitor is small. Several strategies have been developed to eliminate this instability but generally require substantial complexity and critical tuning, even using analog circuits.
At the current state of the art, however, it has become popular to utilize digital control techniques in power converter control since digital circuits provide the advantages of noise immunity, the capability of being re-programmed, automatic tuning and efficiency optimization. However, for a digital implementation of a V2 control architecture, high sampling rate high resolution analog-to-digital (A/D) converters are required to avoid so-called limit cycle oscillation that may result from more coarse quantization of the output voltage of the converter. Suitable A/D converters may also be susceptible to high frequency noise. These and other difficulties and complexities have made a digital implementation of a V2 control architecture for power converters, and buck converters in particular, highly impractical.